Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier
	Wang DH; Ruan J; Li YG; Hou CH; Wang DH Chinese Acad Sci Inst Semicond POB 912 Beijing 100083 Peoples R China.
	2001
会议名称	4th International Conference on ASIC
会议录名称	2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS
页码	624-627
会议日期	OCT 23-25, 2001
会议地点	SHANGHAI, PEOPLES R CHINA
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISBN	0-7803-6677-8
部门归属	chinese acad sci, inst semicond, beijing 100083, peoples r china
摘要	Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.
学科领域	微电子学
主办者	Chinese Inst Electr.; IEEE Beijing Sect.; Natl Nat Sci Fdn China.; Shanghai Municipal Sci & Technol Commiss.
收录类别	CPCI-S
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/13687
专题	中国科学院半导体研究所（2009年前）
通讯作者	Wang DH Chinese Acad Sci Inst Semicond POB 912 Beijing 100083 Peoples R China.
推荐引用方式 GB/T 7714	Wang DH,Ruan J,Li YG,et al. Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2001:624-627.

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