A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation
	Li YJ (Li Yuan-Jin); Zhang WC (Zhang WanCheng); Wu NJ (Wu Nan-Jian); Li, YJ, Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China. E-mail Address: nanjian@red.semi.ac.cn
	2009
会议名称	2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC
会议录名称	2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC
页码	917-920
会议日期	2009
会议地点	Changsha, PEOPLES R CHINA
合作性质	其它
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISBN	978-1-4244-3868-6
摘要	This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.
关键词	Vision Chip Safety Driving Assist Lane Detection Dual-core Processing Element Array
学科领域	微电子学
主办者	IEEE Beijing Sect.; Fudan Univ.; IEEE China Council.; Natl Univ Def Tech.; IEEE CAS, IEEE SSCS.; Chinese Inst Elect.
收录类别	CPCI（ISTP）
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/11145
专题	中国科学院半导体研究所（2009年前）
通讯作者	Li, YJ, Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China. E-mail Address: nanjian@red.semi.ac.cn
推荐引用方式 GB/T 7714	Li YJ ,Zhang WC ,Wu NJ ,et al. A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2009:917-920.

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