An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process
	Li, YL (Li, Y-L.); Feng, P (Feng, P.); Wu, NJ (Wu, N-J.); Li, YL, Chinese Acad Sci, State Key Lab Superlattices & Microstruct, Inst Semicond, Beijing 100864, Peoples R China.
	2008
会议名称	IEEE International Conference of Electron Devices and Solid-State Circuits
会议录名称	EDSSC: 2008 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS
页码	100-103
会议日期	DEC 08-10, 2008
会议地点	Hong Kong, PEOPLES R CHINA
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISBN	978-1-4244-2539-6
部门归属	[li, y-l.; feng, p.; wu, n-j.] chinese acad sci, state key lab superlattices & microstruct, inst semicond, beijing 100864, peoples r china
摘要	This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.
关键词	Voltage
学科领域	微电子学
主办者	IEEE.
收录类别	CPCI-S
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/8368
专题	中国科学院半导体研究所（2009年前）
通讯作者	Li, YL, Chinese Acad Sci, State Key Lab Superlattices & Microstruct, Inst Semicond, Beijing 100864, Peoples R China.
推荐引用方式 GB/T 7714	Li, YL ,Feng, P ,Wu, NJ ,et al. An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2008:100-103.

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