SEMI OpenIR  > 中国科学院半导体研究所(2009年前)
A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction
Yan Xiaozhou; Kuang Xiaofei; Wu Nanjian
2009
Source Publication半导体学报
Volume30Issue:4Pages:99-103
AbstractThis paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dBc/Hz@1MHz.The reference spur is -52 dBc.
metadata_83institute of semiconductors, chinese academy of sciences
Subject Area微电子学
Funding Organizationthe Special Funds for State Key Development for Basic Research of China,国家自然科学基金
Indexed ByCSCD
Language英语
CSCD IDCSCD:3543908
Date Available2010-11-23
Citation statistics
Document Type期刊论文
Identifierhttp://ir.semi.ac.cn/handle/172111/15805
Collection中国科学院半导体研究所(2009年前)
Recommended Citation
GB/T 7714
Yan Xiaozhou,Kuang Xiaofei,Wu Nanjian. A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction[J]. 半导体学报,2009,30(4):99-103.
APA Yan Xiaozhou,Kuang Xiaofei,&Wu Nanjian.(2009).A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction.半导体学报,30(4),99-103.
MLA Yan Xiaozhou,et al."A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction".半导体学报 30.4(2009):99-103.
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